1. Field of the Invention
The present invention relates to a microcomputer with a function of writing data to an embedded flash memory and a function of erasing data therefrom.
2. Description of Related Art
FIG. 11 is a block diagram showing a conventional microcomputer, in which the reference numeral 1 designates an oscillator; 2 and 3 designate a port for connecting the oscillator 1; 4 designates a clock generator for generating clock signals CLK; 5 designates peripheral devices like A/D converters; 6 designates a monitor timer that counts one of the clock signals generated by the clock generator 4, and produces an overflow signal OF when the count value reaches a set value without being reset; 7 designates an interrupt controller for generating an interrupt signal INT to a CPU 12 when the overflow signal OF is produced from the monitor timer 6; 8 designates a personal computer that transmits data to be written into a flash memory 14; 9 designates an interface connected between the personal computer 8 and the microcomputer for receiving and transmitting data between them; and 10 designates a port for connecting the interface 9 to the microcomputer.
The reference numeral 11 designates a RAM in which a program stored in the flash memory 14 is temporarily stored when the CPU 12 writes in the flash memory 14 data transferred from the personal computer 8; 12 designates the CPU that executes programs in response to one of the clock signals generated by the clock generator 4, and carries out, when writing data in the flash memory 14, verification of the written data; 13 designates a flash controller that carries out writing of the data sent from the personal computer 8 into the flash memory 14, and establishes a verification condition by increasing voltages of a sense amplifier and decoder when the CPU 12 issues a verification command; and 14 designates the flash memory for storing programs executed by the CPU 12 and the data transmitted from the personal computer 8.
FIG. 12 is a block diagram showing the detail of the flash controller 13. In FIG. 12, the reference numeral 21 designates a control register that supplies, when a bit "1" is written into it by the CPU 12, a controller 23 with a mode designation signal M indicative of changing the mode of the microcomputer to a data write mode; 22 designates a command register that receives a command sent from the CPU 12 and transfers the command CM to the controller 23; and 23 designates the controller that controls writing in the flash memory 14 the data transmitted from the personal computer 8 when the command register 22 outputs the write command, and establishes the verification condition by increasing the voltages of the sense amplifier and decoder from normal voltages when the CPU 12 outputs the verification command.
Next, the operation of the conventional microcomputer will be described with reference to the timing charts of FIGS. 13(a)-13(d) illustrating the operation of the conventional microcomputer, and to the flowchart of FIG. 14 illustrating it.
First, the CPU 12 executes programs in response to one of the clock signals generated by the clock generator 4. In the course of this, the monitor timer 6, which is provided in preparation for the runaway of the CPU 12 due to a fault of the microcomputer or the like, counts the clock signal, and, outputs the overflow signal OF if the count value reaches the set value without being reset, in which case, the interrupt controller 7 generates the interrupt signal INT to the CPU 12.
When the CPU 12 executes a program stored in the flash memory 14, and if the program contains a data write operation into the flash memory 14, which involves the verification, the CPU 12 transfers the program from the flash memory 14 to the RAM 11 at step ST1 before execution, the reason for which will be described later.
Having transferred the program to the RAM 11, the CPU 12 operates in accordance with the program. When writing data into the flash memory 14, the CPU 12 writes "1" into the control register 21 in the flash controller 13 to have the control register 21 supply the controller 23 with the mode designation signal M so that the controller 23 can recognize that the mode of the microcomputer is shifted to the rewrite mode at step ST2.
Thus, the controller 23 in the flash controller 13 enters into a waiting state in which it accepts a command sent from the CPU 12. The CPU 12 transmits to the command register 22 in the flash controller 13 a command (40H, for example) instructing the controller 23 to write data at step ST3, and then transfers data sent from the personal computer 8 to the controller 23 in the flash controller 13.
Receiving the command from the command register 22 and the data transferred from the personal computer 8, the controller 23 in the flash controller 13 supplies the flash memory 14 with a flash control signal F indicative of the data write, and writes the data into the flash memory 14 as illustrated at position (A) of FIGS. 13(a)-13(d).
When the data has been written into the flash memory 14 in this way, the controller 23 in the flash controller 13 writes "0" in the control register 21 which is kept "1" during the data write operation. The CPU 12 monitors the value stored in the control register 21, and makes a decision whether the data write has been completed or not at steps ST4 and ST5.
Detecting that the value stored in the control register 21 of the flash controller 13 changes to "0", the CPU 12 transmits a verification command (COH, for example) to the command register 22 in the flash controller 13 at step ST6 to make a decision whether or not the data is written correctly into the flash memory 14.
Receiving the verification command from the command register 22, the controller 23 in the flash controller 13 establishes the verification condition by increasing the voltages of the sense amplifier and decoder from their normal voltages as shown at positions (B), (C) and (D) in FIG. 13(d).
These voltages are increased in the verification process to ensure that the data has been written correctly by making a decision whether the data is read correctly under the more strict conditions than usual.
It will now be clear from the foregoing description why the CPU 12 transfers the program to the RAM 11 before writing data into the flash memory 14. This is because once the verification condition has been established, the read condition of the data becomes severer than usual, which will make it difficult for the CPU 12 to read the program correctly, thereby hindering the normal operation.
When the verification condition has been established at step ST7, the CPU 12 reads the data from the flash memory 14, and makes a decision whether the data agrees with an expected value, that is, the data transferred from the personal computer 8. If they agree with each other, it decides that the data is written correctly at step ST8, and then proceeds to the next address at step ST9. On the other hand, if they disagree, it decides that the data is not written correctly at step ST8, and rewrites the data through steps ST3-ST8.
Since the conventional microcomputer has such a configuration, the CPU 12 must read the data from the flash memory 14 when the verification condition has been established. To achieve reading the data, the CPU 12 must read the program correctly at that time. However, since the read condition of the data in the verification condition is severer than usual, it is likely that the program cannot be read correctly from the flash memory 14. Thus, the program must be transferred from the flash memory 14 to the RAM 11 before writing data to the flash memory 14, which presents a problem of complicating the program structure. In addition, the RAM 11 must have a larger capacity by an amount needed for storing the transferred program.